1. Field of the Invention
The present invention relates to a differential amplifier circuit (delta amplifier) that is an analog circuit to be formed on, for example, an LSI (Large Scaled Integrated Circuit) and amplifies a pair of differential signals with selectively switching between the differential signals, and an AD converter apparatus that uses the same. Hereinafter, an analog to time conversion will be referred to as “an AT conversion”, an analog to digital conversion will be referred to as “an AD conversion”, and a time to digital conversion will be referred to as “a TD conversion”. In addition, an analog via time to digital conversion will be referred to as “an ATD conversion”.
2. Description of the Related Art
As a semiconductor process becomes finer, a high-accuracy analog circuit becomes difficult to be realized due to such problems as reduction of a power supply voltage in an analog circuit, deterioration of linearity, deterioration of a signal-to-noise power ratio (hereinafter, referred to as an SNR), and deterioration of a dynamic range. In order to solve these problems, there has been proposed an AD converter that employs a TD converter for measuring an input signal in a time domain (hereinafter, referred to as a first conventional example) (e.g., See Patent Document 1 and Non-Patent Document 1).
According to the first conventional example, the AD converter that employs the TD converter is configured to include a track hold circuit, a comparator, and the TD converter. The comparator compares an input signal with a sinusoidal wave signal serving as a reference signal, and outputs a timing when the input signal is coincident with the reference signal. The TD converter converts the timing (time) data into a digital value. If the reference signal has been already known, an input signal voltage can be fixed based on the timing data, and this leads to realization of AD conversion. In addition, the TD converter is configured to include a digital circuit, and therefore, it benefits from the fine process. Thus, the TD converter can process information in a time domain with higher resolution and higher accuracy even under a low power supply voltage.
In addition, as disclosed in Non-Patent Document 2, an integrating type AD converter according to a second conventional example is characterized in that a comparator receives a ramp wave of an input signal and a ramp wave of a reference signal to detect a timing when the input signal is coincident with the reference signal, and a counter measures the timing (time) data.
Documents related to the present invention are as follows:
Patent Document 1: Japanese Patent Laid-open Publication No. JP-2006-304035-A.
Patent Document 2: Japanese Patent Laid-open Publication No. JP-2005-223888-A.
Patent Document 3: Japanese Patent Laid-open Publication No. JP-2006-157262-A.
Patent Document 4: Japanese Patent Laid-open Publication No. JP-2006-279377-A.
Patent Document 5: Japanese Patent Laid-open Publication No. JP-2008-067050-A.
Non-Patent Document 1: Takanori Komuro et al., “ADC Architecture Using Time-to-Digital Converter”, Technical Papers C of The Institute of Electronics, Information and Communication Engineers, Vol. J90-C, No. 2, pp. 125-133, issued by The Institute of Electronics, Information and Communication Engineers, February 2007.
Non-Patent Document 2: Yoshikazu Nitta et al., “High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor”, Proceedings of 2006 IEEE International Solid-State Circuits Conference (ISSCC 2006), Session 27, Image Sensors, 27.5, pp. 500-501, in San Francisco, U.S.A., Feb. 5-9, 2006.
Non-Patent Document 3: Y. Arai et al., “A CMOS Time to Digital Converter VLSI for High-Energy Physics”, Digest of Technical papers of 1988 Symposium on VLSI Circuits, in Tokyo, Japan, XI-3, pp. 121-122, August 1988.
Non-Patent Document 4: M. Lee et al., “A 9b, 1.25 ps Resolution Coarse-Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue”, Digest of Technical papers of 2007 Symposium on VLSI Circuits, in Kyoto, Japan, No. 16-4, pp. 168-169, June 2007.
Non-Patent Document 5: T. Yoshida et al., “A 1V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique”, IEICE Transactions on Electrons, The Institute of Electronics, Information and Communication Engineers (IEICE), Vol. E89-C, pp. 769-774, June 2006.
According to the first conventional example, the AD converter that employs the TD converter requires a high-accuracy sinusoidal wave signal generator for generating a reference signal. In addition, the AD converter has an input full-scale range which is equal to or less than a power supply voltage. Consequently, there arises such a problem that the circuit becomes poor in SNR and dynamic range if the power supply voltage is reduced because the semiconductor process becomes finer.
In addition, according to the second conventional example, the integrating type AD converter has an input full-scale range which is equal to or less than a power supply voltage. Consequently, the circuit becomes poor in linearity and dynamic range. When the AD converter is realized in an LSI, a ramp signal generator for generating a reference signal is less prone to be formed with higher accuracy, resulting in such a problem that a conversion rate becomes very slow (e.g., several milliseconds).